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Low-, medium- and high-density reset and clock control (RCC)
Bit 26 PINRSTF: PIN reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
RM0008
Bit 25
Reserved, always read as 0.
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2
Reserved, always read as 0.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock
cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
6.3.11
Table 15.
RCC register map
The following table gives the RCC register map and the reset values.
RCC register map and reset values
Offset
Register
0x000
RCC_CR
Reserved
Reserved
HSICAL[7:0]
HSITRIM[4:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0x004
RCC_CFGR
Reserved
MCO [2:0]
PLLMUL[3:0]
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
SW
[1:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x008
RCC_CIR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00C
RCC_APB2RSTR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x010
RCC_APB1RSTR Reser
ved
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
102/995
Doc ID 13902 Rev 9
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